‘cbit’ Dialect

Classical-bit register storage shared by quantum dialects

The CBit dialect represents non-aliasing classical-bit registers whose width, initialization, and public identity remain explicit across quantum IR conversions. It separates source-level classical storage from generic memory lowering.

Operations

cbit.alloc (cbit::AllocOp)

Allocate a classical-bit register

Syntax:

operation ::= `cbit.alloc` `(` qualified($initialization) `)` attr-dict `:` qualified(type($result))

Allocates a static classical-bit register. zero initialization defines every element as false. Reading an element of an undefined register before a store is undefined behavior. The optional mqt.register_name discardable attribute records the source-level name.

Example:

%c = cbit.alloc(#cbit.init<zero>) {mqt.register_name = "c"}
    : !cbit.reg<2>

Attributes:

Attribute	MLIR Type	Description
initialization	::mlir::cbit::InitializationAttr	Classical-bit register initialization

Results:

Result	Description
result	A static classical-bit register

cbit.load (cbit::LoadOp)

Load a classical bit

Syntax:

operation ::= `cbit.load` $reg `[` $index `]` attr-dict `:` qualified(type($reg))

Reads one i1 value from a classical-bit register. A constant index must be within the static register width.

Example:

%bit = cbit.load %c[%index] : !cbit.reg<2>

Operands:

Operand	Description
reg	A static classical-bit register
index	index

Results:

Result	Description
result	1-bit signless integer

cbit.read (cbit::ReadOp)

Read a classical-bit register as an integer

Syntax:

operation ::= `cbit.read` $reg attr-dict `:` qualified(type($reg)) `->` qualified(type($result))

Reads the complete register as an exact-width integer bit pattern. Register element zero is the least-significant result bit, and the result width must equal the static register width.

Example:

%value = cbit.read %c : !cbit.reg<3> -> i3

Operands:

Operand	Description
reg	A static classical-bit register

Results:

Result	Description
result	signless integer

cbit.store (cbit::StoreOp)

Store a classical bit

Syntax:

operation ::= `cbit.store` $value `,` $reg `[` $index `]` attr-dict `:` qualified(type($reg))

Writes one i1 value to a classical-bit register. A constant index must be within the static register width.

Example:

cbit.store %bit, %c[%index] : !cbit.reg<2>

Operands:

Operand	Description
value	1-bit signless integer
reg	A static classical-bit register
index	index

cbit.write (cbit::WriteOp)

Write an integer to a classical-bit register

Syntax:

operation ::= `cbit.write` $value `,` $reg attr-dict `:` qualified(type($value)) `,`
              qualified(type($reg))

Writes a fixed-width integer to the complete register. Integer bit zero is stored in register element zero, and the value width must equal the static register width.

Example:

cbit.write %value, %c : i3, !cbit.reg<3>

Operands:

Operand	Description
value	signless integer
reg	A static classical-bit register

Attributes

InitializationAttr

Classical-bit register initialization

Syntax:

#cbit.init<
  `zero` | `undefined`   # value
>

Parameters:

Parameter	C++ type	Description
value	::mlir::cbit::Initialization	an enum of type Initialization

Types

RegisterType

A static classical-bit register

Syntax:

!cbit.reg<
  int64_t   # width
>

!cbit.reg<N> is a non-aliasing register of N classical bits. N must be positive and is part of the type.

Parameters:

Parameter	C++ type	Description
width	int64_t

Enums

Initialization

Classical-bit register initialization

Cases:

Symbol	Value	String
Zero	0	zero
Undefined	1	undefined

Memory lowering

Use convert-cbit-to-memref when a later pipeline requires generic memory. The pass converts !cbit.reg<N> to memref<Nxi1> in operations, function signatures, calls, branches, and returns. It lowers zero initialization to an allocation followed by false stores. It lowers undefined initialization to an allocation only.

This conversion is one-way. mqt-cc does not infer CBit semantics from an arbitrary memref<Nxi1> because a memref does not record initialization or public-result identity.