Verify Compilation#

QCEC provides a dedicated verify_compilation() method for verifying that a quantum circuit has been compiled correctly based on the methods proposed in [9].

verify_compilation(original_circuit, compiled_circuit, optimization_level=1, ancilla_mode=AncillaMode.NO_ANCILLA, configuration=None, **kwargs)[source]#

Verify compilation flow results.

Similar to verify, but uses a dedicated compilation flow profile to guide the equivalence checking process. The compilation flow profile is determined by the optimization_level and ancilla_mode arguments.

There are two (non-exclusive) ways of configuring the equivalence checking process:

  1. Pass a Configuration instance as the configuration argument.

2. Pass keyword arguments to this function. These are directly incorporated into the Configuration. Any existing configuration is overridden by keyword arguments.

  • original_circuit (QuantumCircuit | str) – The original circuit.

  • compiled_circuit (QuantumCircuit | str) – The compiled circuit.

  • optimization_level (int) – The optimization level used for compiling the circuit (0, 1, 2, or 3). Defaults to 1.

  • ancilla_mode (AncillaMode) – The ancilla mode <.AncillaMode> used for realizing multi-controlled Toffoli gates, as available in Qiskit. Defaults to AncillaMode.NO_ANCILLA.

  • configuration (Optional[Configuration]) – The configuration to use for the equivalence checking process.

  • **kwargs (Unpack[ConfigurationOptions]) – Keyword arguments to configure the equivalence checking process.


Results – The results of the equivalence checking process.


It is essential to include measurements at the end of the circuit, since the equivalence checker uses the measurements to determine the final location of the logical qubits in the compiled circuit. Failing to do so may result in incorrect results because the checker will then simply assume that the logical qubits are mapped to the physical qubits in the same order as they appear in the circuit. Make sure to insert measurements before the circuit is compiled to the target architecture.

class AncillaMode(value, names=None, *, module=None, qualname=None, type=None, start=1, boundary=None)[source]#

Enum for the ancilla mode.

NO_ANCILLA = 'noancilla'#
RECURSION = 'recursion'#
V_CHAIN = 'v-chain'#

Compilation Flow Profile Generation#

QCEC provides dedicated compilation flow profiles for IBM Qiskit which can be used to efficiently verify the results of compilation flow results [9]. These profiles are generated from IBM Qiskit using the generate_profile() method.

generate_profile(optimization_level=1, mode=AncillaMode.NO_ANCILLA, filepath=None)[source]#

Generate a compilation flow profile for the given optimization level and ancilla mode.

  • optimization_level (int) – The IBM Qiskit optimization level to use for the profile (0, 1, 2, or 3). Defaults to 1.

  • mode (AncillaMode) – The ancilla mode <.AncillaMode> used for realizing multi-controlled Toffoli gates, as available in Qiskit. Defaults to AncillaMode.NO_ANCILLA.

  • filepath (Optional[Path]) – The path to the directory where the profile should be stored. Defaults to the profiles directory in the mqt.qcec package.

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