- verify_compilation(original_circuit, compiled_circuit, optimization_level=1, ancilla_mode=AncillaMode.NO_ANCILLA, configuration=None, **kwargs)#
Verify compilation flow results.
verify, but uses a dedicated compilation flow profile to guide the equivalence checking process. The compilation flow profile is determined by the
There are two (non-exclusive) ways of configuring the equivalence checking process:
Configurationinstance as the
2. Pass keyword arguments to this function. These are directly incorporated into the
Configuration. Any existing configuration is overridden by keyword arguments.
int) – The optimization level used for compiling the circuit (0, 1, 2, or 3). Defaults to 1.
ConfigurationOptions]) – Keyword arguments to configure the equivalence checking process.
Results– The results of the equivalence checking process.
It is essential to include measurements at the end of the circuit, since the equivalence checker uses the measurements to determine the final location of the logical qubits in the compiled circuit. Failing to do so may result in incorrect results because the checker will then simply assume that the logical qubits are mapped to the physical qubits in the same order as they appear in the circuit. Make sure to insert measurements before the circuit is compiled to the target architecture.
Compilation Flow Profile Generation#
QCEC provides dedicated compilation flow profiles for IBM Qiskit which can be used to efficiently verify the results of compilation flow results .
These profiles are generated from IBM Qiskit using the
- generate_profile(optimization_level=1, mode=AncillaMode.NO_ANCILLA, filepath=None)#
Generate a compilation flow profile for the given optimization level and ancilla mode.
int) – The IBM Qiskit optimization level to use for the profile (0, 1, 2, or 3). Defaults to 1.
AncillaMode) – The ancilla mode <.AncillaMode> used for realizing multi-controlled Toffoli gates, as available in Qiskit. Defaults to
- Return type: